Introduction
Today’s article will be a short one in which I’ll cover the so called cycle counter register (DWT_CYCCNT), which is present on the BBB’s PRU cores and on other CPUs from the Cortex architecture (See here). However this register is implementation dependent, so it might not be available on chips from some vendors. If this register is not present on a chip, it will always read zero. This register counts the number of cycles for which the PRU has been enabled. Continue reading BeagleBone Black PRU clock cycle counter
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