Today’s article will be a short one in which I’ll cover the so called cycle counter register (DWT_CYCCNT), which is present on the BBB’s PRU cores and on other CPUs from the Cortex architecture (See here). However this register is implementation dependent, so it might not be available on chips from some vendors. If this register is not present on a chip, it will always read zero. This register counts the number of cycles for which the PRU has been enabled.So you can read the register value, execute some other code and read it again. Afterwards you know how many clock cycles it took to execute one command. And since one clock cycle on the BBB’s PRU is exactly 5ns long, you can also tell how long it took to execute the code.
The example code below measures how long it takes to run an operation:
// Make C28 point to the PRU control registers MOV r0, 0x22028 MOV r1, 0x00000220 SBBO r1, r0, 0, 4 // Enable cycle counter by setting bit 3 (COUNTENABLE) of the // control register LBCO r2, C28, 0, 4 SET r2.t3 SBCO r2, C28, 0, 4
After enabling the cycle counter, it is possible to check how long an operation exactly took:
// Get the cycle count before an operation LBCO r3, C28, 0xC, 4 // Execute an operation MOV r10, 100 // Get the cycle count after an operation LBCO r4, C28, 0xC, 4
One thing to note
The register only counts up to 4294967295 ticks (0xFFFFFFFF), it does not wrap. Instead it will clear the COUNTENABLE bit in the PRU control register. To clear the count, the counter has to be reset (disabled and then enabled again) or the PRU has to be disabled. Keep this in mind, when using this register!